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CYM1841A CYM1841B CYM1841C
256K x 32 Static RAM Module
Features
* High-density 8-megabit SRAM module * 32-bit standard footprint supports densities from 16K x 32 through 1M x 32 * High-speed CMOS SRAMs -- Access time of 12 ns * Low active power -- 5.3W (max.) at 25 ns * SMD technology * TTL-compatible inputs and outputs * Low profile -- Max. height of 0.58 in. * Available in ZIP, SIMM, and angled SIMM footprint * 72-pin SIMM version compatible with 1M x 32 (CYM1851) Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Writing to each byte is accomplished when the appropriate Chip Select (CS) and Write Enable (WE) inputs are both LOW. Data on the Input/Output pins (I/O) is written into the memory location specified on the address pins (A0 through A17). Reading the device is accomplished by taking the Chip Select (CS) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the data Input/Output pins (I/O). The data input/output pins stay at the high-impedance state when write enable is LOW or the appropriate chip selects are HIGH. Two pins (PD0 and PD1) are used to identify module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged. The CYM1841A, CYM1841B, and CYM1841C are 100% pin, package, and electrically identical. The CYM1841A utilizes corner power and ground SRAMs, the CYM1841B utilizes 256K x 16 SRAMs, the CYM1841C utilizes center power and ground SRAMs. A 72-pin SIMM is offered for compatibility with the 1M x 32 CYM1851. This version is socket upgradable to the CYM1851. Both the 64-pin and 72-pin SIMM modules are available with either tin-lead or 10 micro-inches of gold flash on the edge contacts.
Functional Description
The CYM1841A/B/C are high-performance 8-megabit static RAM modules organized as 256K words by 32 bits. This module is constructed from eight 256K x 4 SRAMs (1841A/C) or 256K x 16 SRAMs (1841B) in SOJ packages mounted on an epoxy laminate board with pins. Four chip selects (CS1, CS2, CS3, CS4) are used to independently enable the four bytes.
Logic Block Diagram
A0 - A17 OE WE 256K x 4 SRAM CS1 256K x 4 SRAM CS2 256K x 4 SRAM CS3 256K x 4 SRAM CS4
1841A-1 18
PD0 - PD1 - PD2 - PD3 -
GND GND OPEN (72-pin only) OPEN (72-pin only)
4
I/O0 - I/O3
256K x 4 SRAM
4
I/O4- I/O7
4
I/O8 - I/O11
256K x 4 SRAM
4
I/O12 - I/O15
4
I/O16 - I/O19
256K x 4 SRAM
4
I/O20 -I/O23
4
I/O24 - I/O27
256K x 4 SRAM
4
I/O28 -I/O31
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 June 13, 2000
CYM1841A CYM1841B CYM1841C
Logic Block Diagram (1841B)
A0 -A17 OE WE CS1 CS2 CS3 CS4
18
PD0 - PD1 - PD2 - PD3 -
GND GND OPEN (72-pin only) OPEN (72-pin only)
256K x 16 SRAM
8
I/O16-I/O23 I/O24 -I/O31
8
256K x 16 SRAM
8
I/O0 -I/O7 I/O8 -I/O15
1841A-1
8
Selection Guide
1841C-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 12 1600 480 1841B/C-15 15 1600 480 1841A/B/C-20 20 1120 480 1841A/B/C-25 25 960 480 1841A/B/C-35 1841A/B/C-45 35 960 480 45 960 480
Shaded areas contain preliminary information.
2
CYM1841A CYM1841B CYM1841C
Pin Configurations
64-Pin ZIP/SIMM Top View
NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND A19 NC
72-Pin SIMM Top View
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A 15 CS2 CS4 A17 OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31
1841A-3
NC PD2 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 CS4 A17 OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 A18 NC
1841A-2
3
CYM1841A CYM1841B CYM1841C
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... - 55C to +125C Ambient Temperature with Power Applied .................................................... - 10C to +85C Supply Voltage to Ground Potential..................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ..................................................... - 0.5V to +7.0V DC Input Voltage ................................................. - 0.5V to +7.0V
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC 1841C-12 1841B/C-15 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CS Power-Down Current[1] Automatic CS Power-Down Current[1] GND < V I < V CC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, CS < VIL Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -16 -10 Min. 2.4 0.4 VCC 0.8 +16 +10 1600 2.2 -0.5 -16 -10 Max. 1841A/B/C -20 Min. 2.4 0.4 VCC 0.8 +16 +10 1120 2.2 -0.5 -16 -10 Max. 1841A/B/C -25, 35, 45 Min. 2.4 0.4 VCC 0.8 +16 +10 960 Max. Unit V V V V mA mA mA
ISB1
Max. VCC, CS > VIH, Min. Duty Cycle = 100% Max. VCC, CS > VCC 0.2V, VIN > VCC - 0.2V, or VIN < 0.2V
480
480
480
mA
ISB2
240
200
200
mA
Capacitance[2]
Parameter CIN COUT Description Input Capacitance[3] Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 70/20 20 Unit pF pF
Notes: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis. 3. 20 pF on CS, 70 pF all others.
4
CYM1841A CYM1841B CYM1841C
AC Test Loads and Waveforms
R1481 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255 R1481 3.0V 90% GND < 5ns
1841A-4
ALL INPUT PULSES 90% 10% < 5ns
10%
(a)
(b)
1841A-5
Equivalent to: OUTPUT
THEVENIN EQUIVALENT 167 1.73V
5
CYM1841A CYM1841B CYM1841C
Switching Characteristics Over the Operating Range[4]
1841C-12 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tPD tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Output Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z [5] CS HIGH to High Z
[7] [5, 6]
1841B/C-15 Min. 15 Max.
1841A/B/C-20 1841A/B/C-25 Min. 20 Max. Min. 25 20 3 3 20 13 0 0 15 10 10 20 20 20 15 18 0 2 15 13 2 0 25 20 20 0 2 20 15 2 0 15 0 15 20 25 ns ns ns ns ns ns ns ns ns ns 15 25 15 25 Max. Unit ns ns ns ns ns ns ns ns ns
Description
Min. 12
Max.
12 3 12 7 0 7 3 7 12 12 9 9 0 2 10 7 1 0 0 5 15 10 10 0 2 13 8 1 0 0 3 0 3
15 15 8 8 8 15
CS HIGH to Power-Down Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[6]
WRITE CYCLE
7
0
Shaded areas contain preliminary information. Notes: 4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested. 6. tHZCS and tHZWE are specified with C L = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
6
CYM1841A CYM1841B CYM1841C
Switching Characteristics Over the Operating Range[4
1841A/B/C-35 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tPD tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE LOW to High Z CS LOW to Low Z[5] CS HIGH to High Z
[5, 6]
1841A/B/C-45 Min. 45 Max. Unit ns 45 3 45 30 0 15 10 20 45 45 40 40 2 2 35 25 2 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 ns
Description
Min. 35
Max.
35 3 35 25 0 15 10 20 35 35 30 30 2 2 30 20 2 0 0 15
CS HIGH to Power-Down Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[6]
WRITE CYCLE[7]
0
7
CYM1841A CYM1841B CYM1841C
Switching Waveforms
Read Cycle No. 1[8, 9]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1841A-6
Read Cycle No. 2[8, 10]
CS tACS OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCS DATA VALID
1841A-7
tRC
tHZOE tHZCS HIGH IMPEDANCE
Write Cycle No. 1 (WE Controlled)[7]
tWC ADDRESS tSCS CS tAW tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED
1841A-8
tHA tPWE
tHD
tLZWE HIGH IMPEDANCE
Notes: 8. WE is HIGH for read cycle. 9. Device is continuously selected, CS = VIL and OE= VIL. 10. Address valid prior to or coincident with CS transition LOW.
8
CYM1841A CYM1841B CYM1841C
Switching Waveforms (continued)
Write Cycle No. 2 (CS Controlled)[7, 11]
tWC ADDRESS tSA CS tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT HIGH IMPEDANCE DATA UNDEFINED
1841A-9
tSCS
tHA
tHD
Note: 11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
CS H L L L WE X H L H OE X L X H Input/Output High Z Data Out Data In High Z Read Write Deselect Mode Deselect/Power-Down
9
CYM1841A CYM1841B CYM1841C
Ordering Information
Speed (ns) 12 Ordering Code CYM1841CPM-12C CYM1841CP7-12C CYM1841CPZ-12C 15 CYM1841APM15C CYM1841APY-15C CYM1841APT-15C CYM1841AP5-15C CYM1841AP6-15C CYM1841AP7-15C CYM1841AP8-15C CYM1841APN-15C CYM1841APR-15C CYM1841APZ-15C CYM1841BPZ-15C CYM1841BP7-15C 20 CYM1841APM-20C CYM1841APY-20C CYM1841APT-20C CYM1841AP5-20C CYM1841AP6-20C CYM1841AP7-20C CYM1841AP8-20C CYM1841APN-20C CYM1841APR-20C CYM1841APZ-20C CYM1841BPZ-20C CYM1841BP7-20C 25 CYM1841APM-25C CYM1841APY-25C CYM1841APT-25C CYM1841AP5-25C CYM1841AP6-25C CYM1841AP7-25C CYM1841AP8-25C CYM1841APN-25C CYM1841APR-25C CYM1841APZ-25C CYM1841BPZ-25C CYM1841BP7-25C
Shaded areas contain preliminary information.
Package Name PM02 PM04 PZ03 PM02 PM01 PM01 PN04 PM01 PM04 PM04 PN02 PZ01 PZ03 PZ03 PM04 PM02 PM01 PM01 PN04 PM01 PM04 PM04 PN02 PZ01 PZ03 PZ03 PM04 PM02 PM01 PM01 PN04 PM01 PM04 PM04 PN02 PZ01 PZ03 PZ03 PM04
Package Type 64-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic SIMM Module 64-Pin Plastic SIMM Module (gold contacts) 64-Pin Plastic SIMM Module 72-Pin Plastic Angled SIMM Module 72-Pin Plastic Angled SIMM Module (gold contacts) 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 64-Pin Plastic Angled SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic ZIP Module 64-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 64-Pin Plastic SIMM Module 64-Pin Plastic SIMM Module (gold contacts) 64-Pin Plastic SIMM Module 72-Pin Plastic Angled SIMM Module 72-Pin Plastic Angled SIMM Module (gold contacts) 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 64-Pin Plastic Angled SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic ZIP Module 64-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 64-Pin Plastic SIMM Module 64-Pin Plastic SIMM Module (gold contacts) 64-Pin Plastic SIMM Module 72-Pin Plastic Angled SIMM Module 72-Pin Plastic Angled SIMM Module (gold contacts) 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 64-Pin Plastic Angled SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic ZIP Module 64-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module
Operating Range Commercial
Commercial
Commercial
Commercial
10
CYM1841A CYM1841B CYM1841C
Ordering Information (continued)
Speed (ns) 35 Ordering Code CYM1841APM-35C CYM1841APY-35C CYM1841APT-35C CYM1841AP5-35C CYM1841AP6-35C CYM1841AP7-35C CYM1841AP8-35C CYM1841APN-35C CYM1841APR-35C CYM1841APZ-35C CYM1841BPZ-35C CYM1841BP7-35C 45 CYM1841APM-45C CYM1841APY-45C CYM1841APT-45C CYM1841AP5-45C CYM1841AP6-45C CYM1841AP7-45C CYM1841AP8-45C CYM1841APN-45C CYM1841APR-45C CYM1841APZ-45C CYM1841BPZ-45C CYM1841BP7-45C Document #: 38-M-00031-G Package Name PM02 PM01 PM01 PN04 PM01 PM04 PM04 PN02 PZ01 PZ03 PZ03 PM04 PM02 PM01 PM01 PN04 PM01 PM04 PM04 PN02 PZ01 PZ03 PZ03 PM04 Package Type 64-Pin Plastic SIMM Module 64-Pin Plastic SIMM Module (gold contacts) 64-Pin Plastic SIMM Module 72-Pin Plastic Angled SIMM Module 72-Pin Plastic Angled SIMM Module (gold contacts) 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 64-Pin Plastic Angled SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic ZIP Module 64-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 64-Pin Plastic SIMM Module 64-Pin Plastic SIMM Module (gold contacts) 64-Pin Plastic SIMM Module 72-Pin Plastic Angled SIMM Module 72-Pin Plastic Angled SIMM Module (gold contacts) 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 64-Pin Plastic Angled SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic ZIP Module 64-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module Commercial Operating Range Commercial
11
CYM1841A CYM1841B CYM1841C
Package Diagrams
0.125 DIA. + .001 2 PLCS
64-Pin Plastic SIMM Module PM01
3.845 3.855 3.580 3.588
0.330 MAX
0.400
0.525 MAX
0.250 0.080 0.250
V
PIN 1
0.050 TYP
0.62 R + .001 0.250 3.35 (64 PINS)
0.145 REF PIN 64
0.125 DIA. + .001 2 PLCS
64-Pin Plastic SIMM Module PM02
3.845 3.855 3.580 3.588 0.585 0.595
0.350 MAX
0.400
0.250 0.080 0.250 PIN 1
0.050 TYP 3.348 (64 PINS) 3.352
0.62 R + .001 0.250
0.135 REF PIN 64
72-Pin Plastic SIMM Module PM04
12
CYM1841A CYM1841B CYM1841C
Package Diagrams (continued)
64-Pin Plastic Angled SIMM Module PN02
3.845/3.855 3.580/3.588 .350MAX
.670/.680 .397/.403 .245/.255 .061/.063R .050TYP 3.348/3.352 .249/.251 .220REF
PIN1 .075/.085 .245/.255
72-Pin Plastic Angled SIMM Module PN04
64-Pin Plastic ZIP Module PZ01
Bottom View 3.640 3.660 0.330 MAX
0.050
0.050 0.120 0.150
0.500 MAX
0.008 0.014 0.135 0.165 0.015 0.025 0.250 TYP 0.100 TYP 0.050 TYP 0.100 TYP Pin 1 DIMENSIONS IN INCHES MIN. MAX.
13
CYM1841A CYM1841B CYM1841C
Package Diagrams (continued)
64-Pin Plastic ZIP Module PZ03
Bottom View 0.050 3.640 3.660 0.350 MAX
0.050 0.120 0.150
0.575 MAX
0.135 0.165
0.015 0.025
0.250 TYP
0.100 TYP
0.050 TYP 0.100 TYP
Pin 1 DIMENSIONSININCHES MIN. MAX.
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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